Fine-Grain Time Division Multiplexing in FPGAs

Increase in FPGA capacity combined with CMOS technology scaling has resulted in increased demands on the configurable wiring architecture. Modern FPGAs typically give over 50% of the reconfigurable area over to routing resources. Rent’s Rule [1,2] implies that static FPGA wiring is not scalable and we are approaching the point where cross chip communication is impossible within a clock cycle. In order to maintain clock speeds, communications will need to be pipelined; it is a small step to then send the data over a network. Separately, migrating commonly used structures such as processor cores and digital signal processing modules to hard-blocks is a technique employed by most FPGA manufacturers. This serves not only to cut down on power consumption, but also makes more effective use of the chip area. While hard blocks go a long way to accelerate the performance of mapped systems, the reconfigurable FPGA fabric still lags behind. The increasing fault rates of new technologies, as well as other issues, are pushing up the cost of ASIC production. The market for FPGAs is only going to expand as it becomes less economically feasible to produce a hardcore custom solution. FPGAs need to adapt to meet this demand while maintaining the levels of abstraction needed for platform independence and ease of programming.